21EC71 Advanced VLSI
Course Learning Objectives
● Learn overview of VLSI design flow
● Emphasise on Back end VLSI design flow
● Learn basics of verification with reference to System Verilog
SYLLABUS COPY
MODULE - 1
Introduction to ASICs
Full custom, Semi-custom and Programmable ASICs, ASIC Design flow, ASIC cell libraries. CMOS Logic: Data path Logic Cells: Data Path Elements, Adders: Carry skip, Carry bypass, Carry save, Carry select, Conditional sum, Multiplier (Booth encoding), Data path Operators, I/O cells, Cell Compilers.
MODULE - 2
Floor planning and placement
Goals and objectives, Measurement of delay in Floor planning, Floor planning tools, Channel definition, I/O and Power planning and Clock planning. Placement: Goals and Objectives, Min-cut Placement algorithm, Iterative Placement Improvement, Time driven placement methods, Physical Design Flow.
Routing: Global Routing: Goals and objectives, Global Routing Methods, Global routing between blocks, Back annotation
MODULE - 3
Verification Guidelines
The verification process, basic test bench functionality, directed testing, methodology basics, constrained random stimulus, randomization, functional coverage, test bench components, layered testbench.
Data Types
Built in Data types, fixed and dynamic arrays, Queues, associative arrays, linked lists, array methods, choosing a type, creating new types with type def, creating user defined structures, type conversion, Enumerated types, constants and strings, Expression width.
MODULE - 4
Procedural Statements and Routines
Procedural statements, Tasks, Functions and void functions, Task and function overview, Routine arguments, returning from a routine, Local data storage, time values.
Connecting the test bench and design
Separating the test bench and design, The interface construct, Stimulus timing, Interface driving and sampling, System Verilog assertions.
MODULE - 5
Randomization
Introduction, What to randomize? , Randomization in System Verilog, Random number functions, Common randomization problems, Random Number Generators.
Functional Coverage
Coverage types, Coverage strategies, Simple coverage example, Anatomy of Cover group and Triggering a Cover group, Data sampling, Cross coverage, Generic Cover groups, Coverage options, Analyzing coverage data, measuring coverage statistics during simulation.
Course outcome
1. Understand VLSI design flow
2. Describe the concepts of ASIC design methodology
3. Create floor plan including partition and routing with the use of CAD algorithms
4. Will have better insights into VLSI back-end design flow
5. Learn verification basics and System Verilog
Suggested Learning Resources
Text Books
1. Michael John Sebastian Smith, Application – Specific Integrated Circuits, Addison-Wesley Professional, 2005.
2. Chris Spear, System Verilog for Verification – A guide to learning the Test bench language features, Springer Publications, Second Edition, 2010.