21EC731 Advanced Design Tools for VLSI
Course Learning Objectives
● Impart knowledge of EDA tools and methodology for FPGA
● Learn principles of IP core for FPGA and embedded systems
● Infer the concept of machine learning in fabrication and physical design
SYLLABUS COPY
MODULE - 1
Introduction: Introduction, Prologue, EDA
From Methodologies, Algorithms, Tools to Integrated Circuits and Systems, EDA from Halcyon’s Days to the Blooming Paradigm of Chip Industry, Categories of the EDA Tools, Quo Vadis, EDA? The Challenges and Opportunities, Designing the System as SoC Using the Soft IP Cores, Types of IP Cores, Design Issues Pertaining to the Soft IP Cores
Development of FPGA Based Network on Chip for Circumventing Spam
Introduction, Conception of the Spam Mail, FPGA Based Network on Chip for Circumventing Spam, Tools Infrastructure and Design Flow, Introducing Hardware-Software Co-design, Hardware Software Co-design, Framework Proposed in the Present Case Study, Description of System at Higher Level, Resolving the System a Step Down, System Design, Development of Soft IP Core of Bloom Filter, Presenting System Design of Purely Software Modules, Integrating of the Hardware-Software Modules Using EDK
MODULE - 2
Analog Front End and FPGA Based Soft IP Core for ECG Logger
Prior Art, The Very Rationale of the System, Analog Front End of the Setup, VHDL Implementation of the ECG Soft IP Core, ModelSim Simulation Results, Synthesis Results Using Mentor Graphics Tool, Monitoring the ECG Using MODEMBased Setup, ECG Signal Reconstruction Mechanism at the Hospital End, VHDL Listing for Driving the Analog Demultiplexer and Serial DAC from Spartan-3E FPGA, Discussion Regarding the VHDL Implementation, ModelSim Simulation Results, Synthesis Results Using Mentor Graphics Tool: Leonardo Spectrum.
MODULE - 3
FPGA Based Multifunction Interface for Embedded Applications
Introduction, Universal FPGA Based Interface for High End Embedded Applications, Soft IP Core for the LCD Interface, Soft IP Core for the DAC Interface, Handel C Listing of the Soft IP Core for the DAC Interface, Soft IP Core for the Linear Tech LTC6912-1 Dual Amp, Soft IP Core for the ADC Interface, Soft IP Core for the VGA Interface, Soft IP Core for the Keyboard Interface, Triangular Wave Generator Using DAC
MODULE - 4
Machine Learning for Compact Lithographic Process Models
Introduction, The Lithographic Patterning Process, Machine Learning of Compact Process Models, Neural Network Compact Patterning Models.
Machine Learning for Mask Synthesis
Introduction, Machine Learning-Guided OPC, Machine Learning-Guided EPC.
MODULE - 5
Machine Learning in Physical Verification, Mask Synthesis, and Physical Design
Introduction, Machine Learning in Physical Verification, Machine Learning in Mask Synthesis, Machine Learning in Physical Design
Course outcome
1. Demonstrate the EDA methodologies and Tools for FPGA based NoC
2. Interpretation of soft core for ECG logger
3. Interfacing of DAC for embedded Application
4. Interpretation of Machine Learning for fabrication
5. Interpretation of ML in physical design
Suggested Learning Resources
Text Books
1. Rajanish K Kamat, Santosh A Shinde, Pawan K Gaikwad, Hansraj Guhilot, ‘Harnessing VLSI System Design with EDA Tools’, Springer, 2012.
2. Ibrahim (Abe) M Elfadel, Duane S Boning, Xin Li, ‘Machine Learning in VLSI Computer-Aided Design’, Springer, 2011.