21EC733 DSP Algorithms & Architecture

21EC733 DSP Algorithms & Architecture

Course Learning Objectives

● Understand the concepts of digital signal processing techniques.
● Understand the computational building blocks of DSP processors and its speed issues.
● Understand the various addressing modes, peripherals, interrupts and pipelining structure of the TMS320C54xx processor.
● Learn how to interface the external devices to the TMS320C54xx processor in various modes.
● Understand DSP algorithms and applications with their implementation using TMS320C54xx processor.

SYLLABUS COPY

MODULE - 1

Introduction to Digital Signal Processing

Introduction, A Digital Signal – Processing system, Major features of programmable Digital signal processors, The Sampling Process, Discrete Time Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT), Linear Time-Invariant Systems, Digital Filters, Decimation and Interpolation.

MODULE - 2

Architectures for Programmable Digital Signal Processing Devices

Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Speed Issues, Features for External Interfacing.

MODULE - 3

Programmable Digital Signal Processors

Introduction, Commercial Digital Signal-processing Devices, Data Addressing Modes of TMS32OC54XX, Memory Space of TMS32OC54xx Processors, Program Control. Detail Study of TMS320C54X & 54xx Instructions and Programming, On – Chip Peripherals, Interrupts of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor.

MODULE - 4

Implementation of Basic DSP Algorithms

Introduction, The Q – notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters (one example in each case). 

Implementation of FFT Algorithms

Introduction, An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit – Reversed Index. Generation & Implementation on the TMS32OC54xx.

MODULE - 5

Interfacing Memory and Parallel I/O Peripherals to Programmable DSP Devices

Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I/O Direct Memory Access (DMA). 

Interfacing and Applications of DSP Processors

Introduction, Synchronous Serial Interface, A CODEC Interface Circuit, DSP Based Bio-telemetry Receiver, A Speech Processing System, An Image Processing System.

Course outcome

1. Comprehend the knowledge & concepts of digital signal processing techniques.
2. Apply knowledge of various types of addressing modes, interrupts, peripherals and pipelining structure of TMS320C54xx processor.
3. Develop assembly language programs to implement FIR, IIR filters and FFT algorithms.
4. Build the Applications on Programmable DSP devices.

Suggested Learning Resources

Text Book

“Digital Signal Processing”, Avatar Singh and S Srinivasan, Thomson Learning, 2004

Reference Books

1. “Digital Signal Processing: A practical approach”, Ifeachor E C, Jervis B. W Pearson-Education, PHI, 2002.
2. “Digital Signal Processors”, B Venkataramani and M Bhaskar, TMH, 2 Ed., 2010

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